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ltc2301/ltc2305 1 23015fb block diagram features applications description 1-/2-channel, 12-bit adcs with i 2 c compatible interface the ltc ? 2301/ltc2305 are low noise, low power, 1-/2-channel, 12-bit successive approximation adcs with an i 2 c compatible serial interface. these adcs include an internal reference and a fully differential sample-and- hold circuit to reduce common mode noise. the ltc2301/ ltc2305 operate from an internal clock to achieve a fast 1.3s conversion time. the ltc2301/ltc2305 operate from a single 5v supply and draw just 300a at a throughput rate of 1ksps. the adc enters nap mode when not converting, reducing the power dissipation. the ltc2301/ltc2305 are available in small 12-pin 4mm 3mm dfn and 12-pin msop packages. the in- ternal 2.5v reference further reduces pcb board space requirements. the low power consumption and small size make the ltc2301/ltc2305 ideal for battery operated and portable applications, while the 2-wire i 2 c compatible serial interface makes these adcs a good match for space-constrained systems. 12-bit i 2 c adc family input channels 1 2 8 part number ltc2301 ltc2305 ltc2309 integral nonlinearity vs output code (ltc2305) n 12-bit resolution n low power: 1.5mw at 1ksps, 35w sleep mode n 14ksps throughput rate n internal reference n low noise: snr = 73.5db n guaranteed no missing codes n single 5v supply n 2-wire i 2 c compatible serial interface with 9 addresses plus one global for synchronization n fast conversion time: 1.3s n 1-channel (ltc2301) and 2-channel (ltc2305) versions n unipolar or bipolar input ranges (software selectable) n internal conversion clock n guaranteed operation from C40c to 125c (msop package) n 12-pin 4mm 3mm dfn and 12-pin msop packages n industrial process control n motor control n accelerometer measurements n battery operated instruments n isolated and/or remote data acquisition n power supply monitoring l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 23015 ta01a + C 12-bit sar adc analog input mux analog input 0v to 4.096v unipolar 2.048v bipolar i 2 c port internal 2.5v ref 0.1f 10f 2.2f v ref refcomp scl sda ad1 ad0 ch0(in + ) ch1(in + ) pin names in parentheses refer to ltc2301 10f 0.1f v dd ltc2301 ltc2305 gnd 5v output code 0 inl (lsb) 1.00 0.75 0.25 C0.25 C0.75 0.50 0.00 C0.50 C1.00 2048 1024 3072 23015 ta01b 4096
ltc2301/ltc2305 2 23015fb absolute maximum ratings supply voltage (v dd ) ................................ C0.3v to 6.0v analog input voltage (note 3) ch0(in + ), ch1(in C ), ref, refcomp .............(gnd C 0.3v) to (v dd + 0.3v) digital input voltage ..........(gnd C 0.3v) to (v dd + 0.3v) digital output voltage .......(gnd C 0.3v) to (v dd + 0.3v) (notes 1, 2) pin configuration order information power dissipation ...............................................500mw operating temperature range ltc2301c/ltc2305c ............................... 0c to 70c ltc2301i/ltc2305i .............................. C40c to 85c ltc2301h/ltc2305h (note 13) ......... C40c to 125c storage temperature range ................... C65c to 150c lead free finish tape and reel part marking * package description temperature range ltc2301cde#pbf ltc2301cde#trpbf 2301 12-lead (3mm 4mm) plastic dfn 0c to 70c ltc2301ide#pbf ltc2301ide#trpbf 2301 12-lead (3mm 4mm) plastic dfn C40c to 85c ltc2305cde#pbf ltc2305cde#trpbf 2305 12-lead (3mm 4mm) plastic dfn 0c to 70c ltc2305ide#pbf ltc2305ide#trpbf 2305 12-lead (3mm 4mm) plastic dfn C40c to 85c ltc2301cms#pbf ltc2301cms#trpbf 2301 12-lead plastic msop 0c to 70c ltc2301ims#pbf ltc2301ims#trpbf 2301 12-lead plastic msop C40c to 85c ltc2301hms#pbf ltc2301hms#trpbf 2301 12-lead plastic msop C40c to 125c ltc2305cms#pbf ltc2305cms#trpbf 2305 12-lead plastic msop 0c to 70c ltc2305 ltc2301 12 11 10 9 8 7 13 1 2 3 4 5 6 ad0 ad1 v dd gnd refcomp v ref gnd sda scl gnd ch0 ch1 top view de package 12-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 43c/w exposed pad (pin 13) is gnd, must be soldered to pcb 12 11 10 9 8 7 13 1 2 3 4 5 6 ad0 ad1 v dd gnd refcomp v ref gnd sda scl gnd in + in C top view de package 12-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 43c/w exposed pad (pin 13) is gnd, must be soldered to pcb ltc2305 ltc2301 1 2 3 4 5 6 gnd sda scl gnd ch0 ch1 12 11 10 9 8 7 ad0 ad1 v dd gnd refcomp v ref top view ms package 12-lead plastic msop t jmax = 150c, ja = 130c/w 1 2 3 4 5 6 gnd sda scl gnd in + in C 12 11 10 9 8 7 ad0 ad1 v dd gnd refcomp v ref top view ms package 12-lead plastic msop t jmax = 150c, ja = 130c/w
ltc2301/ltc2305 3 23015fb order information lead free finish tape and reel part marking * package description temperature range ltc2305ims#pbf ltc2305ims#trpbf 2305 12-lead plastic msop ?40c to 85c ltc2305hms#pbf ltc2305hms#trpbf 2305 12-lead plastic msop ?40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ converter and multiplexer characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (note 5) l 0.4 1 lsb differential linearity error l 0.3 1 lsb bipolar zero error (note 6) l 0.5 8 lsb bipolar zero error drift 0.002 lsb/c unipolar zero error (note 6) l 0.7 6 lsb unipolar zero error drift 0.002 lsb/c unipolar zero error match (ltc2305) 0.1 1 lsb bipolar full-scale error external reference (note 7) refcomp = 4.096v (note 7) l l 1 0.9 10 9 lsb lsb bipolar full-scale error drift external reference 0.05 lsb/c unipolar full-scale error external reference (note 7) refcomp = 4.096v (note 7) l l 0.5 0.7 10 6 lsb lsb unipolar full-scale error drift external reference 0.05 lsb/c unipolar full-scale error match (ltc2305) 0.1 2 lsb analog input symbol parameter conditions min typ max units v in + absolute input range (ch0, ch1, in + ) (note 8) l ?0.05 refcomp v v in ? absolute input range (ch0, ch1, in ? ) unipolar (note 8) bipolar (note 8) l ?0.05 ?0.05 0.25 ? refcomp 0.75 ? refcomp v v v in + ? v in ? input differential voltage range v in = v in + ? v in ? (unipolar) v in = v in + ? v in ? (bipolar) l 0 to refcomp refcomp/2 v v i in analog input leakage current l 1 a c in analog input capacitance sample mode hold mode 55 5 pf pf cmrr input common mode rejection ratio 70 db the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4)
ltc2301/ltc2305 4 23015fb dynamic accuracy symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 1khz l 71 73.4 db snr signal-to-noise ratio f in = 1khz l 71 73.5 db thd total harmonic distortion f in = 1khz l C91 C77 db sfdr spurious free dynamic range f in = 1khz, first 5 harmonics l 79 92 db channel-to-channel isolation f in = 1khz C109 db full linear bandwidth f in = 1khz 700 khz C3db input linear bandwidth (note 10) 25 mhz aperture delay 13 ns transient response full-scale step 240 ns the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c and a in = C1dbfs. (notes 4,9) internal reference characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 4) parameter conditions min typ max units v ref output voltage i out = 0 l 2.46 2.50 2.54 v v ref output tempco i out = 0 25 ppm/c v ref output impedance C0.1ma i out 0.1ma 8 k v refcomp output voltage i out = 0 4.096 v v ref line regulation v dd = 4.75v to 5.25v 0.8 mv/v i 2 c inputs and digital outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 4) symbol parameter conditions min typ max units v ih high level input voltage l 2.85 v v il low level input voltage l 1.5 v v iha high level input voltage for address pins a1, a0 l 4.75 v v ila low level input voltage for address pins a1, a0 l 0.25 v r inh resistance from a1, a0 to v dd to set chip address bit to 1 l 10 k r inl resistance from a1, a0 to gnd to set chip address bit to 0 l 10 k r inf resistance from a1, a0 to gnd or v dd to set chip address bit to float l 2m i i digital input current v in = v dd l C10 10 a v hys hysteresis of schmitt trigger inputs (note 8) l 0.25 v v ol low level output voltage (sda) i = 3ma l 0.4 v t of output fall time v in(min) to v il(max) bus load c b 10pf to 400pf (note 11) l 20 + 0.1c b 250 ns t sp input spike suppression l 50 ns c cax external capacitance load on chip address pins (a1, a0) for valid float l 10 pf
ltc2301/ltc2305 5 23015fb power requirements symbol parameter conditions min typ max units v dd supply voltage l 4.75 5 5.25 v i dd supply current nap mode sleep mode 14ksps sample rate slp bit = 0, conversion done slp bit = 1, conversion done l l l 2.3 225 7 3.5 400 15 ma a a p d power dissipation nap mode sleep mode 14ksps sample rate slp bit = 0, conversion done slp bit = 1, conversion done l l l 11.5 1.125 35 17.5 2 75 mw mw w the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) i 2 c timing characteristics symbol parameter conditions min typ max units f scl scl clock frequency l 400 khz t hd(sda) hold time (repeated) start condition l 0.6 s t low low period of the scl pin l 1.3 s t high high period of the scl pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time for sda/scl signals (note 11) l 20 + 0.1c b 300 ns t f fall time for sda/scl signals (note 11) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a second start condition l 1.3 s the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) adc timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units f smpl throughput rate (successive reads) l 14 ksps t conv conversion time l 1.3 1.6 s t acq acquisition time (note 8) l 240 ns t refwake refcomp wakeup time (note 12) c refcomp = 10f, c ref = 2.2f 200 ms
ltc2301/ltc2305 6 23015fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above v dd , they will be clamped by internal diodes. these products can handle input currents greater than 100ma below ground or above v dd without latchup. note 4: v dd = 5v, f smpl = 14khz, internal reference unless otherwise noted. note 5: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: bipolar zero error is the offset voltage measured from C0.5 lsb when the output code ? ickers between 0000 0000 0000 and 1111 1111 1111. unipolar zero error is the offset voltage measured from 0.5 lsb when the output code ? ickers between 0000 0000 0000 and 0000 0000 0001. note 7: full-scale bipolar error is the worst-case of Cfs or fs untrimmed deviation from ideal ? rst and last code transitions and includes the effect of offset error. unipolar full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. note 8: guaranteed by design, not subject to test. note 9: all speci? cations in db are referred to a full-scale 2.048v input with a 2.5v reference voltage. note 10: full linear bandwidth is de? ned as the full-scale input frequency at which the sinad degrades to 60db or 10 bits of accuracy. note 11: c b = capacitance of one bus line in pf (10pf c b 400pf) note 12: refcomp wakeup time is the time required for the refcomp pin to settle within 0.5 lsb at 12-bit resolution of its ? nal value after waking up from sleep mode. note 13: high temperatures degrade operating lifetimes. operating lifetime is derated at temperatures greater than 105c. electrical characteristics
ltc2301/ltc2305 7 23015fb typical performance characteristics integral nonlinearity vs output code differential nonlinearity vs output code 1khz sine wave 8192 point fft plot supply current vs sampling frequency offset error vs temperature full-scale error vs temperature supply current vs temperature sleep current vs temperature analog input leakage current vs temperature (ltc2301) t a = 25c, v dd = 5v, f smpl = 14ksps, unless otherwise noted. output code 0 inl (lsb) 1.00 0.75 0.25 C0.25 C0.75 0.50 0.00 C0.50 C1.00 2048 1024 3072 23015 g01 4096 output code 0 dnl (lsb) 1.00 0.75 0.25 C0.25 C0.75 0.50 0.00 C0.50 C1.00 2048 1024 3072 23015 g02 4096 frequency (khz) 0 magnitude (db) 0 C70 C60 C50 C40 C30 C20 C10 C90 C110 C130 C80 C100 C120 C140 5 1234 6 23015 g03 7 snr = 73.2 db sinad = 73.1 db thd = C90db sampling frequency (ksps) supply current (ma) 23015 g04 2.5 1.0 1.5 2.0 0.5 0 0.1 10 100 1 temperature (c) C50 offset error (lsb) 1.5 1.0 0.0 0.5 C0.5 C1.0 50 0 100 23015 g05 125 25 C25 75 bipolar unipolar temperature (c) C50 full-scale error (lsb) 4 2 C2 0 C4 C6 50 0 100 23015 g06 125 25 C25 75 bipolar unipolar temperature (c) C50 supply current (ma) 2.4 2.2 1.6 1.8 1.4 50 0 100 23015 g07 125 25 C25 75 temperature (c) C50 sleep current (a) 10 8 2 4 6 0 50 0 100 23015 g08 125 25 C25 75 temperature (c) C50 leakage current (na) 1000 800 900 700 200 100 400 300 600 500 0 50 0 100 23015 g09 125 25 C25 75
ltc2301/ltc2305 8 23015fb typical performance characteristics integral nonlinearity vs output code differential nonlinearity vs output code 1khz sine wave 8192 point fft plot supply current vs sampling frequency offset error vs temperature full-scale error vs temperature supply current vs temperature sleep current vs temperature analog input leakage current vs temperature (ltc2305) t a = 25c, v dd = 5v, f smpl = 14ksps, unless otherwise noted. output code 0 inl (lsb) 1.00 0.75 0.25 C0.25 C0.75 0.50 0.00 C0.50 C1.00 2048 1024 3072 23015 g10 4096 output code 0 dnl (lsb) 1.00 0.75 0.25 C0.25 C0.75 0.50 0.00 C0.50 C1.00 2048 1024 3072 23015 g11 4096 frequency (khz) 0 magnitude (db) 0 C70 C60 C50 C40 C30 C20 C10 C90 C110 C130 C80 C100 C120 C140 5 1234 6 23015 g12 7 snr = 73.2 db sinad = 73.1 db thd = C90db sampling frequency (ksps) supply current (ma) 23015 g13 2.5 1.0 1.5 2.0 0.5 0 0.1 10 100 1 temperature (c) C50 offset error (lsb) 1.0 0.0 0.5 C0.5 50 0 100 23015 g14 125 25 C25 75 bipolar unipolar temperature (c) C50 full-scale error (lsb) 4 2 C2 0 C4 C6 50 0 100 23015 g15 125 25 C25 75 bipolar unipolar temperature (c) C50 supply current (ma) 2.4 2.2 1.6 1.8 1.4 50 0 100 23015 g16 125 25 C25 75 temperature (c) C50 sleep current (a) 10 8 2 4 6 0 50 0 100 23015 g17 125 25 C25 75 temperature (c) C50 leakage current (na) 1000 800 900 700 200 100 400 300 600 500 0 50 0 100 23015 g18 125 25 C25 75 ch(on) ch(off)
ltc2301/ltc2305 9 23015fb pin functions gnd (pins 1, 4, 9): ground. all gnd pins must be con- nected to a solid ground plane. sda (pin 2): bidirectional serial data line of the i 2 c in- terface. in transmitter mode (read), the conversion result is output at the sda pin, while in receiver mode (write), the d in word is input at the sda pin to con? gure the adc. the pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to v dd ) during the data output mode. scl (pin 3): serial clock pin of the i 2 c interface. the ltc2301 can only act as a slave and the scl pin only ac- cepts an external serial clock. data is shifted into the sda pin on the rising edges of the scl clock and output through the sda pin on the falling edges of the scl clock. in + , in C (pins 5, 6): positive (in + ) and negative (in C ) differential analog inputs. v ref (pin 7): 2.5v reference output. bypass to gnd with a minimum 2.2f ceramic capacitor. the internal refer- ence may be overdriven by an external 2.5v reference at this pin. refcomp (pin 8): reference buffer output. bypass to gnd with 10f and 0.1f ceramic capacitors in parallel. nominal output voltage is 4.096v. the internal reference buffer driving this pin is disabled by grounding v ref , al- lowing refcomp to be overdriven by an external source (see figure 5c). v dd (pin 10): 5v analog supply. the range of v dd is 4.75v to 5.25v. bypass v dd to gnd with 10f and 0.1f ceramic capacitors in parallel. ad1 (pin 11): chip address control pin. this pin is con- ? gured as a three-state (low, high, ? oating) address control bit for the device i 2 c address. see table 2 for address selection. ad0 (pin 12): chip address control pin. this pin is con- ? gured as a three-state (low, high, ? oating) address control bit for the device i 2 c address. see table 2 for address selection. gnd (pin 13 C dfn package only): exposed pad ground. must be soldered directly to ground plane. (ltc2301)
ltc2301/ltc2305 10 23015fb pin functions gnd (pins 1, 4, 9): ground. all gnd pins must be con- nected to a solid ground plane. sda (pin 2): bidirectional serial data line of the i 2 c in- terface. in transmitter mode (read), the conversion result is output at the sda pin, while in receiver mode (write), the d in word is input at the sda pin to con? gure the adc. the pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to v dd ) during the data output mode. scl (pin 3): serial clock pin of the i 2 c interface. the ltc2305 can only act as a slave and the scl pin only ac- cepts an external serial clock. data is shifted into the sda pin on the rising edges of the scl clock and output through the sda pin on the falling edges of the scl clock. ch0-ch1 (pins 5, 6): channel 0 and channel 1 analog inputs. ch0 and ch1 can be con? gured as single-ended or differential input channels. see the analog input multi- plexer section. v ref (pin 7): 2.5v reference output. bypass to gnd with a minimum 2.2f ceramic capacitor. the internal refer- ence may be overdriven by an external 2.5v reference at this pin. refcomp (pin 8): reference buffer output. bypass to gnd with 10f and 0.1f ceramic capacitors in parallel. nominal output voltage is 4.096v. the internal reference buffer driving this pin is disabled by grounding v ref , al- lowing refcomp to be overdriven by an external source (see figure 5c). v dd (pin 10): 5v analog supply. the range of v dd is 4.75v to 5.25v. bypass v dd to gnd with 10f and 0.1f ceramic capacitors in parallel. ad1 (pin 11): chip address control pin. this pin is con- ? gured as a three-state (low, high, ? oating) address control bit for the device i 2 c address. see table 2 for address selection. ad0 (pin 12): chip address control pin. this pin is con- ? gured as a three-state (low, high, ? oating) address control bit for the device i 2 c address. see table 2 for address selection. gnd (pin 13 C dfn package only): exposed pad ground. must be soldered directly to ground plane. (ltc2305)
ltc2301/ltc2305 11 23015fb functional block diagram 23015 bd + C 12-bit sar adc analog input mux i 2 c port internal 2.5v ref gain = 1.6384x v ref refcomp scl sda ad1 ad0 ch0(in + ) ch1(in C ) pin names in parentheses refer to ltc2301 v dd ltc2301 ltc2305 8k gnd timing diagram sda scl ssrps t hd(sda) s = start, sr = repeated start, p = stop t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t r t f t f t high 23015 td de? nition of timing for fast/standard mode devices on the i 2 c bus
ltc2301/ltc2305 12 23015fb applications information overview the ltc2301/ltc2305 are low noise, 1-/2-channel, 12-bit successive approximation register (sar) a/d converters with an i 2 c compatible serial interface. the ltc2301/ ltc2305 both include a precision internal reference. the ltc2305 includes a 2-channel analog input multiplexer (mux) while the ltc2301 includes an input mux that allows the polarity of the differential input to be selected. these adcs can operate in either unipolar or bipolar mode. uni- polar mode should be used for single-ended operation with the ltc2305, since single-ended input signals are always referenced to gnd. a sleep mode option is also provided to further reduce power during inactive periods. the ltc2301/ltc2305 communicate through a 2-wire i 2 c compatible serial interface. conversions are initiated by signaling a stop condition after the part has been successfully addressed for a read/write operation. the device will not acknowledge an external request until the conversion is ? nished. after a conversion is ? nished, the device is ready to accept a read/write request. once the ltc2301/ltc2305 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (scl). there is no latency in the conversion result. there are 12 bits of output data fol- lowed by four trailing zeros. data is updated on the falling edges of scl, allowing the user to reliably latch data on the rising edge of scl. a write operation may follow the read operation by using a repeat start or a stop condi- tion may be given to start a new conversion. by selecting a write operation, these adcs can be programmed by a 6-bit d in word. the d in word con? gures the mux and programs various modes of operation. during a conversion, the internal 12-bit capacitive charge- redistribution dac output is sequenced through a succes- sive approximation algorithm by the sar starting from the most signi? cant bit (msb) to the least signi? cant bit (lsb). the sampled input is successively compared with binary weighted charges supplied by the capacitive dac using a differential comparator. at the end of a conver- sion, the dac output balances the analog input. the sar contents (a 12-bit data word) that represent the sampled analog input are loaded into 12 output latches that allow the data to be shifted out via the i 2 c interface. programming the ltc2301 and ltc2305 the software compatible ltc2301/ltc2305/ltc2309 fam- ily features a 6-bit d in word to program various modes of operation. dont care bits (x) are ignored. the sda data bits are loaded on the rising edge of scl during a write operation, with the s/d bit loaded on the ? rst rising edge and the slp bit on the sixth rising edge (see figure 7b in the i 2 c interface section). the input data word for the ltc2305 is de? ned as follows: s/d o/s x x uni slp s/d = single-ended/ differential bit o/s = odd/ sign bit uni = unipolar/ bipolar bit slp = sleep mode bit for the ltc2301, the input word is de? ned as: x o/s x x uni slp analog input multiplexer the analog input mux is programmed by the s/d and o/s bits of the d in word for the ltc2305 and the o/s bit of the d in word for the ltc2301. table 1 and table 2 list the mux con? gurations for all combinations of the con? guration bits. figure 1a shows several possible mux con? gurations and figure 1b shows how the mux can be recon? gured from one conversion to the next. table 1. channel con? guration for the ltc2305 s/d o/s ch0 ch1 00+C 01C+ 10+ 11 +
ltc2301/ltc2305 13 23015fb applications information table 2. channel con? guration for the ltc2301 o/s in + in C 0+C 1C+ figure 1a. example mux con? gurations figure 1b. changing the mux assignment on the fly ch0 ch1 gnd ( C ) 2 single-ended + 1 differential + ( C ) + C ( + ) 1 differential + (C) C (+) { { 23015 f01a ch0 ch1 ch0 ch1 ltc2305 ltc2305 ltc2301 gnd ( C ) 1st conversion 2nd conversion + C + C {{ ch0 ch1 ch0 ch1 23015 f01b ltc2305 ltc2305 driving the analog inputs the analog inputs of the ltc2301/ltc2305 are easy to drive. each of the analog inputs of the ltc2305 (ch0 and ch1) can be used as single-ended input relative to gnd or as a differential pair. the analog inputs of the ltc2301 (in + , in C ) are always con? gured as a differential pair. regardless of the mux con? guration, the + and C inputs are sampled at the same instant. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold cir- cuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors during the acquire mode. in conversion mode, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, the adc inputs can be driven directly. otherwise, more acquisition time should be allowed for a source with higher impedance. input filtering the noise and distortion of the input ampli? er and other circuitry must be considered since they will add to the adc noise and distortion. therefore, noisy input circuitry should be ? ltered prior to the analog inputs to minimize noise. a simple 1-pole rc ? lter is suf? cient for many applications. the analog inputs of the ltc2301/ltc2305 can be modeled as a 55pf capacitor (c in ) in series with a 100 resistor (r on ), as shown in figure 2a. c in gets switched to the selected input once during each conversion. large ? lter rc time constants will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle to 12-bit resolution within the acquisition time (t acq ) if dc accuracy is important. when using a ? lter with a large c filter value (e.g. 1f), the inputs do not completely settle and the capacitive input switching currents are averaged into a net dc current ( idc ). in this case, the analog input can be modeled by an equivalent resistance (r eq = 1/(f smpl ? c in )) in series with an ideal voltage source (v refcomp /2), as shown in figure 2b.
ltc2301/ltc2305 14 23015fb applications information the magnitude of the dc current is then approximately i dc = (v in C v refcomp /2)/r eq , which is roughly proportional to v in . to prevent large dc drops across the resistor r filter , a ? lter with a small resistor and large capacitor should be chosen. when running at the maximum throughput rate of 14ksps, the input current equals 1.5a at v in = 4.096v, which amounts to a full-scale error of 0.5 lsbs when using a ? lter resistor (r filter ) of 333. applications requiring lower sample rates can tolerate a larger ? lter resistor for the same amount of full-scale error. figures 3a and 3b show respective examples of input ? ltering for single-ended and differential inputs. for the single-ended case in figure 4a, a 50 source resistor and a 2000pf capacitor to ground on the input will limit the input bandwidth to 1.6mhz. high quality capacitors and resistors should be used in the rc ? lter since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating figure 2a. analog input equivalent circuit figure 2b. analog input equivalent circuit for large filter capacitances v in input ch0, ch1, in + , in C r on = 100 c in = 55pf c filter r source 23015 f02a ltc2301 ltc2305 v in input (ch0, ch1, in + , in C ) r eq = 1/(f smpl ? c in ) v refcomp /2 c filter r filter i dc 23015 f02b ltc2301 ltc2305 + C and from damage that may occur during soldering. metal ? lm surface mount resistors are much less susceptible to both problems. dynamic performance fast fourier transform (fft) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling figure 3a. optional rc input filtering for single-ended input figure 3b. optional rc input filtering for differential inputs 23015 f03a ch0, ch1 ltc2305 refcomp 2000pf 0.1f 10f 50 analog input 1000pf 23015 f03b ch0, in + ch1, in C ltc2301 ltc2305 refcomp 1000pf 1000pf 0.1f 10f 50 50 differential analog inputs
ltc2301/ltc2305 15 23015fb applications information frequency. figure 4 shows a typical sinad of 73.2db with a 14khz sampling rate and a 1khz input. a snr of 73.3db can be achieved with the ltc2301/ltc2305. figure 4. 1khz sine wave 8192 point fft plot total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency ( fsmpl /2). thd is expressed as: thd = 20log v 2 2 + v 3 2 + v 4 2 ... + v n 2 v 1 where v1 is the rms amplitude of the fundamental fre- quency and v2 through v n are the amplitudes of the second through nth harmonics. internal reference the ltc2301/ltc2305 have an on-chip, temperature compensated bandgap reference that is factory trimmed to 2.5v (refer to figure 5a). it is internally connected to a reference ampli? er and is available at v ref (pin 7). v ref should be bypassed to gnd with a 2.2f ceramic capacitor to minimize noise. an 8k resistor is in series with the output so that it can be easily overdriven by an external reference if more accuracy and/or lower drift are required, as shown in figure 5b. the reference ampli? er gains the v ref volt- age by 1.638 to 4.096v at refcomp . to compensate the reference ampli? er, bypass refcomp with a 10f ceramic capacitor in parallel with a 0.1f ceramic capacitor for best noise performance. the internal reference buffer can also be overdriven from 1v to v dd with an external reference at refcomp , as shown in figure 5c. to do so, v ref must be grounded to disable the reference buffer. this will result in an input range of 0v to v refcomp in unipolar mode and 0.5 ? v refcomp in bipolar mode. r2 r3 reference amp 0.1f 10f 2.2f refcomp gnd v ref r1 8k 2.5v 4.096v ltc2301 ltc2305 23015 f05a bandgap reference figure 5a. ltc2301/ltc2305 reference circuit figure 5b. using the lt1790a-2.5 as an external reference figure 5c. overdriving refcomp using the lt1790a-4.096 0.1f 10f 23015 f05b lt1790a-2.5 v out v in 5v v ref ltc2301 ltc2305 gnd refcomp 2.2f 0.1f 0.1f 10f 23015 f05c lt1790a-4.096 v out v in 5v v ref ltc2301 ltc2305 gnd refcomp 0.1f frequency (khz) 0 magnitude (db) 0 C70 C60 C50 C40 C30 C20 C10 C90 C110 C130 C80 C100 C120 C140 5 1234 6 23015 f04 7 snr = 73.2 db sinad = 73.1 db thd = C90db
ltc2301/ltc2305 16 23015fb applications information internal conversion clock the internal conversion clock is factory trimmed to achieve a typical conversion time (t conv ) of 1.3s and a maximum conversion time of 1.6s over the full operating temperature range. i 2 c interface the ltc2301/ltc2305 communicate through an i 2 c in- terface. the i 2 c interface is a 2-wire open-drain interface supporting multiple devices and multiple masters on a single bus. the connected devices can only pull the serial data line (sda) low and can never drive it high. sda is required to be externally connected to the supply through a pull-up resistor. when the data line is not being driven low, it is high. data on the i 2 c bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. the v dd power should not be removed from the ltc2301/ ltc2305 when the i 2 c bus is active to avoid loading the i 2 c bus lines through the internal esd protection diodes. each device on the i 2 c bus is recognized by a unique address stored in the device and can only operate either as a transmitter or receiver, depending on the function of the device. a device can also be considered as a master or a slave when performing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit the transfer. devices addressed by the master are considered slaves. the ltc2301/ltc2305 can only be addressed as slaves. once addressed, they can receive con? guration bits (d in word) or transmit the last conversion result. the serial clock line (scl) is always an input to the ltc2301/ltc2305 and the serial data line (sda) is bidirectional. these devices support the standard mode and the fast mode for data transfer speeds up to 400kbits/s (see timing diagram section for de? nition of the i 2 c timing). the start and stop conditions referring to figure 6, a start (s) condition is generated by transitioning sda from high to low while scl is high. the bus is considered to be busy after the start condition. when the data transfer is ? nished, a stop (p) condition is generated by transitioning sda from low to high while scl is high. the bus is free after a stop condition is generated. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the repeated start timing is functionally identical to the start and is used for writing and reading from the device before the initiation of a new conversion. data transferring after the start condition, the i 2 c bus is busy and data transfer can begin between the master and the addressed slave. data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ack) bit. the master releases the sda line during the ninth scl clock cycle. the slave device can issue an ack by pulling sda low or issue a not acknowledge (nack) by leaving the sda line high impedance (the external pull-up resistor will hold the line high). change of data only occurs while the scl line is low. data format after a start condition, the master sends a 7-bit ad- dress followed by a read/write (r/w) bit. the r/w bit is 1 for a read request and 0 for a write request. if the 7-bit address matches one of the ltc2301/ltc2305s 9 pin- selectable addresses (see table 2), the adc is selected. when the adc is addressed during a conversion, it will not acknowledge r/w requests and will issue a nack by leaving the sda line high. if the conversion is complete, the ltc2301/ltc2305 issues an ack by pulling the sda line low. the ltc2301/ltc2305 has two registers. the 12-bit wide output register contains the last conversion result. the 6-bit wide input register con? gures the input mux and the operating mode of the adc. figure 6. timing diagrams of start and stop conditions s start condition stop condition p 23015 f06 sda scl sda scl
ltc2301/ltc2305 17 23015fb applications information output data format the output register contains the last conversion result. after each conversion is completed, the device automati- cally enters either nap or sleep mode depending on the setting of the slp bit (see nap mode and sleep mode sections). when the ltc2301/ltc2305 is addressed for a read operation, it acknowledges by pulling sda low and acts as a transmitter. the master/receiver can read up to two bytes from the ltc2301/ltc2305. after a complete read operation of 2 bytes, a stop condition is needed to initiate a new conversion. the device will nack subsequent read operations while a conversion is being performed. the data output stream is 16 bits long and is shifted out on the falling edges of scl (see figure 7a). the ? rst bit is the msb and the 12th bit is the lsb of the conversion result. the remaining four bits are zero. figures 13 and 14 are the transfer characteristics for the bipolar and unipolar modes. data is output on the sda line in 2s complement format for bipolar readings and in straight binary for unipolar readings. input data format when the ltc2301/ltc2305 is addressed for a write op- eration, it acknowledges by pulling sda low during the low period before the 9th cycle and acts as a receiver. the master/transmitter can then send 1 byte to program the device. the input byte consists of the 6-bit d in word followed by two bits that are ignored by the adc and are considered dont cares (x) (see figure 7b). the input bits are latched on the rising edge of scl during the write operation. figure 7a. timing diagram for reading from the ltc2301/ltc2305 12 a6 sda start by master ack by adc ack by master nack by master stop by master conversion initiated scl scl (continued) a5 a4 a3 a2 a1 a0 r/ w 3456789 123456789 123456789 23015 f07a b11 b10 read 1 byte b9 b8 b7 most significant data byte b6 b5 b4 ? ? ? ? ? ? sda (continued) ? ? ? ? ? ? b3 b2 b1 b0 least significant data byte read 1 byte address frame figure 7b. timing diagram for writing to the ltc2301/ltc2305 12 a6 sda start by master ack by adc ack by adc conversion initiated stop by master scl a5 a4 a3 a2 a1 a0 r/ w 3456789 123456789 23015 f07b s/d o/s write 1 byte x x uni d in word slp x x address frame note: s/d bit is a dont care (x) for the ltc2301
ltc2301/ltc2305 18 23015fb applications information after power-up, the adc initiates an internal reset cycle which sets the d in word to all 0s (s/d=o/s=uni=slp=0). a write operation may be performed if the default state of the adcs con? guration is not desired. otherwise, the adc must be properly addressed and followed by a stop condition to initiate a conversion. initiating a new conversion the ltc2301/ltc2305 awakens from either nap or sleep when properly addressed for a read/write operation. a stop command may then be issued after performing the read/write operation to trigger a new conversion. issuing a stop command after the 8th scl clock pulse of the address frame and before the completion of a read/write operation will also initiate new conversion, but the output result may not be valid due to lack of adequate acquisition time (see acquisition section). ltc2301/ltc2305 address the ltc2301/ltc2305 have two address pins (ad0 and ad1) that may be tied high, low or left ? oating to enable one of the 9 possible addresses (see table 2). in addition to the con? gurable addresses listed in table 2, the ltc2301/ltc2305 also contain a global address (1101011) which may be used for synchronizing multiple ltc2301/ltc2305s or other i 2 c ltc230x sar adcs (see synchronizing multiple ltc2301/ltc2305s with global address call section). table 2. address assignment ad1 ad0 address low low 0001000 low float 0001001 low high 0001010 float high 0001011 float float 0011000 float low 0011001 high low 0011010 high float 0011011 high high 0101000 continuous read in applications where the same input channel is sampled each cycle, conversions can be continuously performed and read without a write cycle (see figure 8). the d in word remains unchanged from the last value written into the device. if the device has not been written to since power- up, the d in word defaults to all 0s (s/d=o/s=uni=slp=0). at the end of a read operation, a stop condition may be given to start a new conversion. at the conclusion of the conversion cycle, the next result may be read using the method described above. if the conversion cycle is not concluded and a valid address selects the device, the ltc2301/ltc2305 generates a nack signal indicating the conversion cycle is in progress. figure 8. consecutive reading with the same con? guration s conversion nap data output conversion conversion nap data output r ack read 7-bit address p s r ack 23015 f08 read 7-bit address p
ltc2301/ltc2305 19 23015fb applications information continuous read/write once the conversion cycle is complete, the ltc2301/ ltc2305 can be written to and then read from using the repeated start (sr) command. figure 9 shows a cycle which begins with a data write, a repeated start, followed by a read and concluded with a stop command. after all 16 bits are read out, a conversion may be initiated by issuing a stop command. the following conversion will be performed using the newly programmed data. synchronizing multiple ltc2301/ltc2305s with a global address call in applications where several ltc2301/ltc2305s or other i 2 c sar adcs from linear technology corporation are used on the same i 2 c bus, all converters can be synchro- nized through the use of a global address call. prior to issuing the global address call, all converters must have completed a conversion cycle. the master then issues a start, followed by the global address 1101011, and a write request. all converters will be selected and acknowl- edge the request. the master then sends a write byte (optional) followed by the stop command. this will update the channel selection (optional) and simultaneously initi- ate a conversion for all adcs on the bus (see figure 10). in order to synchronize multiple converters without chang- ing the channel, a stop command may be issued after acknowledgement of the global write command. global read commands are not allowed and the converters will nack a global read request. nap mode the adcs enter nap mode after a conversion is complete (t conv ) if the slp bit is set to a logic 0. the supply current decreases to 225a in nap mode between conversions, thereby reducing the average power dissipation as the sample rate decreases. for example, the ltc2301/ltc2305 draw an average of 300a at a 1ksps sampling rate. the ltc2301/ltc2305 keep only the reference (v ref ) and reference buffer (refcomp) circuitry active when in nap mode. figure 9. write, read, start conversion figure 10. synchronize multiple ltc2301/ltc2305s with a global address call s conversion nap data input address conversion data output w ack write 7-bit address sr r ack 23015 f09 read 7-bit address p s sda scl conversion nap ltc2301/ltc2305 data output conversion of all ltc2301/05s w ack write (optional) global address p ltc2301/ltc2305 ltc2301/ltc2305 23015 f10
ltc2301/ltc2305 20 23015fb applications information sleep mode the adcs enter sleep mode after a conversion is complete (t conv ) if the slp bit is set to a logic 1. the adcs draw only 7a in sleep mode, provided that none of the digital inputs are switching. when the ltc2301/ltc2305 are properly addressed, the adcs are released from sleep mode and require 200ms (t refwake ) to wake up and charge the respective 2.2f and 10f bypass capacitors on the v ref and refcomp pins. a new conversion should not be initiated before this time, as shown in figure 11. acquisition the ltc2301/ltc2305 begin acquiring the input signal at different instances depending on whether a read or write operation is being performed. if a read operation is being performed, acquisition of the input signal begins on the rising edge of the 9th clock pulse following the address frame, as shown in figure 12a. if a write operation is being performed, acquisition of the input signal begins on the falling edge of the sixth clock cycle after the d in word has been shifted in, as shown in figure 12b. the ltc2301/ltc2305 will acquire the signal from the input channel that was most recently programmed by the d in word. a minimum of 240ns is required to acquire the input signal before initiating a new conversion. board layout and bypassing to obtain the best performance, a printed circuit board with a solid ground plane is required. layout for the printed board should ensure digital and analog signal lines are s conversion sleep t refwake conversion r/ w ack 7-bit address p 23015 f11 figure 11. exiting sleep mode and starting a new conversion figure 12a. timing diagram showing acquisition during a read operation 12 a6 sda scl a5 a4 a3 a2 a1 a0 r/ w 3456789 12 b11 acquisition begins t acq 23015 f12a b10 figure 12b. timing diagram showing acquisition during a write operation 12 a2 a1 a0 r/ w sda scl s/d o/s x x uni x x 345 56789 6789 acquisition begins t acq 23015 f12b slp
ltc2301/ltc2305 21 23015fb separated as much as possible. care should be taken not to run any digital signals alongside an analog signal. all analog inputs should be shielded by gnd. v ref , refcomp and v dd should be bypassed to the ground plane as close to the pin as possible. maintaining a low impedance path applications information figure 15a. top silkscreen for the common return of these bypass capacitors is es- sential to the low noise operation of the adc. these traces should be as wide as possible. see figures 15aC15e for a suggested layout. figure 13. bipolar transfer characteristics (2s complement) figure 14. unipolar transfer characteristics (straight binary) input voltage (v) 0v output code (twos complement) C1 lsb 23015 f13 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 C 1lsb Cfs/2 fs = 4.096v 1lsb = fs/2 n 1lsb = 1mv input voltage (v) output code 23015 f14 111...111 111...110 100...001 100...000 000...000 000...001 011...110 011...111 fs C 1lsb 0v unipolar zero fs = 4.096v 1lsb = fs/2 n 1lsb = 1mv
ltc2301/ltc2305 22 23015fb applications information figure 15c. layer 2 ground plane figure 15d. layer 3 power plane figure 15e. bottom side figure 15b. topside
ltc2301/ltc2305 23 23015fb package description de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695) 4.00 p 0.10 (2 sides) 3.00 p 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.70 p 0.10 0.75 p 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 s 45 o chamfer pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 p 0.05 0.70 p 0.05 3.60 p 0.05 package outline 3.30 p 0.10 0.25 p 0.05 0.50 bsc 1.70 p 0.05 3.30 p 0.05 0.50 bsc 0.25 p 0.05
ltc2301/ltc2305 24 23015fb ms package 12-lead plastic msop (reference ltc dwg # 05-08-1668 rev ?) package description msop (ms12) 1107 rev ? 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 11 10 9 8 7 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.42 p 0.038 (.0165 p .0015) typ 0.65 (.0256) bsc 4.039 p 0.102 (.159 p .004) (note 3) 0.1016 p 0.0508 (.004 p .002) 123456 3.00 p 0.102 (.118 p .004) (note 4) 0.406 p 0.076 (.016 p .003) ref 4.90 p 0.152 (.193 p .006)
ltc2301/ltc2305 25 23015fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 8/10 revised typical performance characteristics curves g03 and g12 7, 8 revised v ref , refcomp and v dd descriptions in pin functions section 9, 10 revised figure 4 in applications information section 15 revised figures 5a, 5b and 5c, internal reference section and i 2 c interface section in applications information 15, 16 changed nak command to nack 16, 17 (revision history begins at rev b)
ltc2301/ltc2305 26 23015fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0810 rev b ? printed in usa related parts typical application part number description comments ltc1417 14-bit, 400ksps serial adc 20mw, unipolar or bipolar, internal reference, ssop-16 package ltc1468/lt1469 single/dual 90mhz, 22v/s, 16-bit accurate op amps low input offset: 75v/125v ltc1609 16-bit, 200ksps serial adc 65mw, con? gurable bipolar and unipolar input ranges, 5v supply ltc1790 micropower low dropout reference 60a supply current, 10ppm/c, sot-23 package ltc1850/ltc1851 10-bit/12-bit, 8-channel, 1.25msps adc parallel output, programmable mux and sequencer, 5v supply ltc1852/ltc1853 10-bit/12-bit, 8-channel, 400ksps adc parallel output, programmable mux and sequencer, 3v or 5v supply ltc1860/ltc1861 12-bit, 1-/2-channel 250ksps adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 3v, 12-bit, 1-/2-channel 150ksps adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1863/ltc1867 12-/16-bit, 8-channel 200ksps adc 6.5mw, unipolar or bipolar, internal reference, ssop-16 package ltc1863l/ltc1867l 3v, 12-/16-bit, 8-channel 175ksps adc 2mw, unipolar or bipolar, internal reference, ssop-16 package ltc1864/ltc1865 16-bit, 1-/2-channel 250ksps adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 3v, 16-bit, 1-/2-channel 150ksps adc in msop 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc2302/ltc2306 12-bit, 1-/2-channel 500ksps spi adcs in 3mm 3mm dfn 14mw at 500ksps, single 5v supply, software compatible with ltc2308 ltc2308 12-bit, 8-channel 500ksps spi adc 5v, internal reference, 4mm 4mm qfn package, software compatible with ltc2302/ltc2306 ltc2309 12-bit, 8-channel adc with i 2 c interface 5v, internal reference, 4mm 4mm qfn and 20-pin tssop packages, software compatible with ltc2301/ltc2305 ltc2451/ltc2453 easy-to-use, ultra-tiny 16-bit i 2 c delta sigma adcs 2 lsb inl, 50na sleep current, 60hz output rate, 3mm 2mm dfn package, single-ended/differential inputs ltc2487/ltc2489/ ltc2493 2-/4-channel easy drive i 2 c delta sigma adcs 16-/24-bits, pga and temp sensor, 4mm 3mm dfn packages ltc2495/ltc2497/ ltc2499 8-/16-channel easy drive i 2 c delta sigma adcs 16-/24-bits, pga and temp sensor, 5mm 7mm qfn packages driving the ltc2305 with 10v input signals using a precision attenuator 23015 ta02 i 2 c port analog input mux refcomp control logic (fpga, cpld, dsp , etc) internal 2.5v ref v dd 5v 10v C10v 10v input signal gnd ltc2305 0.1 f 12-bit sar adc + C 2.2 f 10 f 0.1 f 10 f 1 f 0.1 f 47 p f 7 45 6 8 1 9 10 100 450k lt1790-2.5 5v in out gnd 50k 150k 450k 150k 450k 4pf v ref sda scl 1.7k 1.7k ad1 ad0 ch0 ch0 ch1 450k 4pf 3 2 50k C + lt1991

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